Flash memory devices, for example, NAND flash memory devices, are generally accessed via a two-way 8-bit or 16-bit I/O bus. NAND-flash devices are not accessed in the same manner as other general memory devices. Reading the NAND-flash memory typically requires that the host system know the page size and the I/O bus size of the NAND-flash memory device connected to it.
Generally, the NAND-flash memory is organized as an array having a plurality of blocks. Small sized NAND-flash devices may have a capacity of 8 MB, 16 MB, 32 MB, or 64 MB. A large sized NAND-flash devices may have a capacity of 128 MB, 256 MB, 512 MB, or 1 GB. In small sized NAND-flash devices, each block comprises 16 pages and each page is divided into a data area of 512 bytes and a spare area of 16 bytes. In large sized NAND-flash devices, each block comrpises 64 pages, and each page is divided into a data area of 2048 bytes and a spare area of 64 bytes. If the host microprocessor system is unable to correctly recognize the installed NAND-flash, accessing of data in the NAND-flash may be impossible.
Typically, the read access and the write access take place at the page level, with a “page” being a memory area of 512 bytes (in case of Small Page architecture), 2048 bytes (in case of Large Page architecture), or 4096 bytes (in case of Very Large Page architecture). Typically, host systems that utilize NAND-flash devices connected to them identify the type of NAND-flash by utilizing a static device ID look-up table. Unfortunately, this conventional way of identification of the type of NAND-flash device has drawbacks.
A first deficiency with the conventional method of NAND-flash identification is that for host systems to be able to utilize NAND-flash of new characteristics, as new vendors as well as long established vendors release memory devices of new sizes and specifications, the system updates its device ID look-up table with the newest releases of NAND-flash products. Updating the device ID look-up table represents a non-trivial maintenance effort of the host system.
An attendant drawback with the conventional NAND-flash identification method becomes evident as more vendors release newer NAND-flash products that forces static device ID look-up tables that contain the NAND-flash ID list to continually grow because identification information about new commercial NAND-flash devices is continually added. Accordingly, larger memory capacities are allocated to the static device ID look-up tables.
Normally, the static device ID table is stored in the BOOT code or in on-chip RON code. Storing the static device ID table in BOOT code or in on-chip ROM code is per se a costly configuration operation, made even more complicated by the fact that static device ID tables are becoming larger and larger. A flexible access method for a large number of types of NAND flash memory devices is desirable. Preferably, such an access method should be capable of supporting future types of memory chips without updating hardware.
U.S. Patent Application Publication No. 2005/0180206 to Randell et al discloses a technique for identifying whether a NAND flash memory device is accessible through a 8-bit or a 16-bit bus without reading the identification code of the device. Nothing on the use of knowing the page size of the memory device is disclosed, least of all of, an ability of identifying the size without knowing it from recorded data.
In an attempt to provide an approach to this deficiency, U.S. Patent Application Publication No. 2007/0061498 to Chua et al. discloses a method of identifying a NAND flash memory device without reading its identification code. The method comprises reading at least a whole memory page as if the memory device had a certain page size and was accessible through a data bus of a certain size (8-bit or 16-bit), and if a certain identification pattern (already stored in the memory) is correctly read, then the memory device has that certain page size and is accessible through a data bus of that certain size, otherwise trying with another combination of page size and data bus size.
Theoretically, this method is effective but burdensome because it uses reading data of a whole memory page plus at least another 32 bytes of data in order to locate the page boundary, for each trial combination, and eventually repeating the same trial process until the correct combination of supposed page size of the memory and data bus size is struck.
Moreover, the disclosure is silent about the way the spare areas of the memory device are accounted for. It is not explained if and how the disclosed method would recognize the page size and the data bus size of a NAND flash memory device should the read memory page contain failed memory cells.